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general description the MAX17232/max17233 offers dual synchronous step- down dc-dc controllers with integrated mosfets. they operates over a 3.5v to 36v input voltage range with 42v input transient protection, and can operate in dropout condition by running at 95% duty cycle. the controllers can generate fixed output voltages of 3.3v/5v, along with the capability to program the output voltage between 1v to 10v. these devices use a current-mode-control architecture. the devices can be operated in pulse-width modulation (pwm) or pulse-frequency modulation (pfm) control schemes. pwm operation provides constant frequency operation at all loads, and is useful in applications sensitive to switching frequency. pfm operation disables negative inductor current and additionally skips pulses at light loads for high efficiency. the low-resistance, on-chip mosfets ensure high efficiency at full load and simplify the layout. the devices are available in a 28-pin tqfn-ep package with exposed pad, and are specified for operation over -40c to +85c. applications distributed supply regulation wall transformer regulation general-purpose point-of-load benefts and features eliminates external components and reduces total cost ? no schottky-synchronous operation for high effciency and reduced cost ? simple external rc compensation for stable operation at any output voltage ? all-ceramic capacitor solution: ultra-compact layout ? 180 out-of-phase operation reduces output ripple and enables cascaded power supplies reduces number of dc-dc controllers to stock ? fixed output voltage with 1% accuracy (5v/3.3v) or externally resistor adjustable (1v to 10v) ? 220khz to 2.2mhz adjustable frequency with external synchronization ? frequency synchronization input reduces power dissipation ? 92% peak effciency ? 8a (typ) in shutdown ? 20a (typ) quiescent current in pfm mode operates reliably ? 42v input voltage transient protection ? cycle-by-cycle current limit, thermal shutdown ? supply overvoltage and undervoltage lockout ? power-ok monitor ? reduced emi emission with spread-spectrum control ? 50ns (typ) minimum on-time guarantees pwm operation at low duty cycle at 2.2mhz 19-8366; rev 0; 2/16 ordering information and selector guide appears at end of data sheet. evaluation kit available MAX17232/max17233 3.5vC36v, 2.2mhz, synchronous dual buck controller with 20a quiescent current
typical application circuit MAX17232 max17233 pgood1 fb1 fb2 *dcr sense is also an option. dl1 dh1 lx1 bst1 l1 r cs1 * cout1 out1 cs1 cin out1 out1 pgood2 pgnd1 lx2 extvcc out1 in dh2 dl2 v bat l2 r cs2 * r pgood1 cout2 out2 cs2 bias bst2 cs1 cs1 en1 en2 out2 cs2 cs2 out2 fsync fosc comp1 agnd pgnd2 pgnd2 comp2 maxim integrated 2 MAX17232/max17233 3.5vC36v, 2.2mhz, synchronous dual buck controller with 20a quiescent current www.maximintegrated.com
in, en1, en2, term to pgnd_ ........................... -0.3v to +42v cs1, cs2, out1, out2 to agnd ........................ -0.3v to +11v cs1 to out1 ........................................................ -0.2v to +0.2v cs2 to out2 ........................................................ -0.2v to +0.2v bias, fsync, fosc to agnd ............................ -0.3v to +6.0v comp1, comp2 to agnd .................................. -0.3v to +6.0v fb1, fb2, extvcc to agnd .............................. -0.3v to +6.0v dl_ to pgnd_ ..................................................... -0.3v to +6.0v bst_, to lx_ ....................................................... -0.3v to + 6.0v dh_ to lx_ .......................................................... -0.3v to + 6.0v lx_ to pgnd_ ....................................................... -0.3v to +42v pgnd_ to agnd .................................................. -0.3v to +0.3v pgood1, pgood2 to agnd.......... ............. ......-0.3v to +6.0v continuous power dissipation (t a = +70c) tqfn (derate 28.6mw/nc above +70c)............ . 2285.7mw operating temperature range. .......................... -40c to +85c junction temperature range .......................................... +150c storage temperature range ............................ -65c to +150c lead temperature (soldering, 10s) ................................. +300c soldering temperature (reflow)...................................... . +260c tqfn junction-to-ambient thermal resistance ( ja ) .......... 35c/w junction-to-case thermal resistance ( jc ) ................. 3c/w (note 1) (v in = 14v, v bias = 5v, c bias = 6.8f, t a = t j = -40c to +85c, unless otherwise noted. typical values are at t a = +25c under normal conditions, unless otherwise noted.) (note 2) note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to ab solute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics electrical characteristics parameter symbol conditions min typ max unit synchronous step-down dc-dc controllers supply voltage range v in normal operation 3.5 36 v t < 1s 42 output overvoltage threshold fb rising (note 3) +10 +15 +20 % fb falling +5 +10 +15 supply current i in v en1 = v en2 = 0v, t a = +25c 8 20 a v en1 = v en2 = 0v, t a = +125c 20 v en1 = 5v, v out1 = 5v, v en2 = 0v; v extvcc = 5v, no switching 30 40 v en2 = 5v, v out2 = 3.3v; v en1 = 0v, v extvcc = 3.3v, no switching 20 30 v en1 = v en2 = 5v, v out1 = 5v, v out2 = 3.3v, v extvcc = 3.3v, no switching 25 40 buck 1 fixed output voltage v out1 v fb1 = v bias , pwm mode 4.95 5 5.05 v v fb1 = v bias , skip mode 4.95 5 5.075 buck 2 fixed output voltage v out2 v fb2 = v bias , pwm mode 3.234 3.3 3.366 v v fb2 = v bias , skip mode 3.234 3.3 3.4 output voltage adjustable range buck 1, buck 2 1 10 v maxim integrated 3 MAX17232/max17233 3.5vC36v, 2.2mhz, synchronous dual buck controller with 20a quiescent current www.maximintegrated.com
(v in = 14v, v bias = 5v, c bias = 6.8f, t a = t j = -40c to +85c, unless otherwise noted. typical values are at t a = +25c under normal conditions, unless otherwise noted.) (note 2) electrical characteristics (continued) parameter symbol conditions min typ max unit regulated feedback voltage v fb1,2 0.99 1.0 1.01 v feedback leakage current i fb1,2 t a = +25c 0.01 1 a feedback line regulation error v in = 3.5v to 36v, v fb = 1v 0.001 %/v transconductance (from fb_ to comp_) g m v fb = 1v, v bias = 5v 1200 2400 s dead time max17233: dl_ low to dh_ high 35 ns max17233: dh_ low to dl_ high 60 MAX17232: dl_ low to dh_ high 60 MAX17232: dh_ low to dl_ high 100 maximum duty cycle buck 1, buck 2 95 98.5 % minimum on-time t on(min) buck 1, buck 2 50 ns pwm switching frequency f sw max17233 1 2.2 mhz MAX17232 0.2 1 buck 2 switching frequency max17233atit+, max17233batiu+ only 1/2f sw mhz switching frequency accuracy max17233: r fosc = 13.7k?, v bias = 5v 1.98 2.2 2.42 mhz MAX17232: r fosc = 80.6k?, v bias = 5v 360 400 440 khz spread-spectrum range spread spectrum enabled 6 % fsync input fsync frequency range max17233: minimum sync pulse of 100ns 1.2 2.4 mhz MAX17232: minimum sync pulse of 400ns 240 1200 khz fsync switching thresholds high threshold 1.5 v low threshold 0.6 cs current-limit voltage threshold v limit1,2 v cs C v out , v bias = 5v, v out 2.5v 64 80 96 mv skip mode threshold 15 mv soft-start ramp time buck 1 and buck 2, fxed soft-start time regardless of frequency 2 6 10 ms phase shift between buck1 and buck 2 180 lx1, lx2 leakage current v in = 6v, v lx _ = v in , t a = +25c 0.01 a dh1, dh2 pullup resistance v bias = 5v, i dh_ = -100ma 10 20 ? dh1, dh2 pulldown resistance v bias = 5v, i dh_ = +100ma 2 4 ? dl1, dl2 pullup resistance v bias = 5v, i dl_ = -100ma 4 8 ? dl1, dl2 pulldown resistance v bias = 5v, i dl_ = +100ma 1.5 3 ? maxim integrated 4 MAX17232/max17233 3.5vC36v, 2.2mhz, synchronous dual buck controller with 20a quiescent current www.maximintegrated.com
(v in = 14v, v bias = 5v, c bias = 6.8f, t a = t j = -40c to +85c, unless otherwise noted. typical values are at t a = +25c under normal conditions, unless otherwise noted.) (note 2) note 2: limits are 100% production tested at t a = +25c. limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. typical values are at t a = +25c. note 3: overvoltage protection is detected at the fb1/fb2 pins. if the feedback voltage reaches overvoltage threshold of fb1/fb2 + 15% (typ), the corresponding controller stops switching. the controllers resume switching once the output drops below fb1/fb2 + 10% (typ). note 4: guaranteed by design; not production tested. parameter symbol conditions min typ max unit pgood1, pgood2 threshold p good_h % of v out_ , rising 85 90 95 % p good_f % of v out_ , falling 80 85 90 pgood1, pgood2 leakage current v pgood1,2 = 5v, t a = +25c 0.01 1 a pgood1, pgood2 startup delay time buck 1 and buck 2 after soft-start is complete 64 cycles pgood1, pgood2 debounce time fault detection 8 20 50 s internal ldo: bias internal bias voltage v in > 6v 4.75 5 5.25 v bias uvlo threshold v bias rising 3.1 3.4 v v bias falling 2.7 2.9 hysteresis 0.2 v external v cc v th,extvcc extv cc rising, hyst = 110mv 3.0 3.2 v thermal overload thermal-shutdown temperature (note 4) +170 c thermal-shutdown hysteresis (note 4) 20 c en logic input high threshold 1.8 v low threshold 0.8 v input current t a = +25c 1 a electrical characteristics (continued) maxim integrated 5 MAX17232/max17233 3.5vC36v, 2.2mhz, synchronous dual buck controller with 20a quiescent current www.maximintegrated.com
(t a = +25c, unless otherwise noted.) typical operating characteristics quiescient current vs. temperature temperature (c) supply current (a) 0 20 40 60 80 100 120 140 -20 20 10 50 40 30 60 0 -60 -40 toc03 v en1 = v bat v en2 = 0v extvcc = v out1 v en1 = 0v v en2 = v bat extvcc = v out2 no load startup sequence (v fsync = 0v) toc01 v bat 5v/div v out1 2v/div v out2 2v/div v pgood1 5v/div v pgood2 5v/div 2ms/div buck1 efficiency toc05 i out1 (a) 1.0e+00 1.0e-02 1.0e-04 10 20 30 40 50 60 70 80 90 100 0 1.0e-06 1.0e-01 1.0e-03 1.0e-05 1.0e+01 f sw = 2.2mhz l = 2.2h v bat = 14v v out1 = 5v skip mode extvcc = v out1 extvcc = gnd extvcc = v out2 extvcc = gnd pwm mode efficiency (%) quiescient current vs. supply voltage supply voltage ( v) supply current (a) 15 20 25 30 35 40 10 20 10 70 60 50 40 30 80 0 0 5 toc04 buck 1 extvcc = v out1 buck 2 extvcc = v out2 full load startup sequence (v fsync = 0v) toc02 v bat 5v/div v out1 2v/div v out2 2v/div i out1 2a /div i out2 2a /div v pgood1 5v/div v pgood2 5v/div 4ms/div buck2 efficiency toc06 i out2 (a) efficiency (%) 1.0e+00 1.0e-02 1.0e-04 10 20 30 40 50 60 70 80 90 100 0 1.0e-06 1.0e-01 1.0e-03 1.0e-05 1.0e+01 f sw = 2.2mhz l = 2.2h v bat = 14v v out2 = 3.3v skip mode pwm mode extvcc = v out2 extvcc = gnd extvcc = v out2 extvcc = gnd maxim integrated 6 MAX17232/max17233 3.5vC36v, 2.2mhz, synchronous dual buck controller with 20a quiescent current www.maximintegrated.com
(t a = +25c, unless otherwise noted.) typical operating characteristics (continued) switching frequency vs. load current toc07 load current (a) switching frequency (mhz) 5 4 3 2 1 2.12 2.14 2.16 2.18 2.20 2.22 2.24 2.26 2.28 2.30 2.10 0 6 buck 1 buck 2 switching frequency vs. r fosc (max17233) r fosc (k?) switching frequency (mhz) 15 25 30 2.4 2.2 2.0 1.8 1.6 1.4 1.2 0 0 20 toc08 v bias = 3.3v v bias = 5v switching frequency vs. r fosc (MAX17232) toc09 r fosc (k?) switching frequency (mhz) 160 150 130 140 60 70 80 90 100 110 120 40 50 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 0.2 30 170 v bias = 5v v bias = 3.3v switching frequency vs. temperature temperature (c) switching frequency (mhz) 20 40 80 120 -20 -40 0 60 100 140 2.10 2.05 2.30 2.25 2.15 2.35 2.20 2.40 2.00 -60 toc10 r fosc = 13.7k? external sync transition toc12 v lx1 10v/div v lx2 10v/div v sync 2v/div 400ns/div load transient response toc11 v out1 100mv/div i out1 1a /div 400s/div dips and drops toc13 v bat 10v/div v pgood1 5v/div v out1 5v/div 40ms/div maxim integrated g 7 MAX17232/max17233 3.5vC36v, 2.2mhz, synchronous dual buck controller with 20a quiescent current www.maximintegrated.com
(t a = +25c, unless otherwise noted.) typical operating characteristics (continued) buck 1 load regulation i out (a) v out (v) 2 3 4 5 1 6 4.992 4.991 4.996 4.995 4.993 4.997 4.994 4.998 4.989 4.990 0 toc18 v sync = v bias v sync = v bias buck 2 load regulation i out (a) vout (v) 2 3 4 5 6 1 3.294 3.293 3.296 3.295 3.292 3.291 3.290 3.289 3.297 0 toc19 v sync = v bias vout vs. temperature temperature (c) vout (%nominal) -20 0 20 40 60 80 100 120 140 -40 99.95 99.85 99.90 100.05 100.00 100.10 99.70 99.75 99.80 -60 toc20 vout1 vout2 extvcc = v gnd v sync = v bias i out_ = 0a short circuit response toc16 i out1 2a /div v pgood1 2v/div v out1 1v/div 200s/div line transient toc14 v bat 10v/div v pgood2 5v/div v out2 1v/div 100ms/div output overvoltage response toc17 v pgood1 2v/div v out1 1v/div 1s/div slow v in ramp toc15 v bat 5v/div v pgood2 5v/div v pgood1 5v/div v out2 2v/div v out1 2v/div 10s/div maxim integrated 8 MAX17232/max17233 3.5vC36v, 2.2mhz, synchronous dual buck controller with 20a quiescent current www.maximintegrated.com
(t a = +25c, unless otherwise noted.) typical operating characteristics (continued) spectral energy density vs. frequency frequency (hz) output spectrum (dbv) 350,000 400,000 450,000 500,000 20 30 40 10 0 -10 50 300,000 toc25 measured on the MAX17232etis+ spectral energy density vs. frequency frequency (hz) output spectrum (dbv) 1000k 1100k 1200k 900k 15 20 35 30 25 10 5 -10 -5 0 40 800k toc26 measured at v out2 on the max17233etiu+ spectral energy density vs. frequency frequency (hz) output spectrum (dbv) 2200k 2400k 2600k 2000k 15 20 30 25 10 5 -10 -5 0 35 1800k toc27 measured on the max17233etis+ minimum on-time (buck 1) toc23 v bat 5v/div v out1 1v/div 200ns /div i out1 = 300ma fb1 line regulation vsup (v) vout (v) 10 15 20 25 30 35 40 5 0.995 1.005 1.000 1.010 0.990 0 toc21 v out1 = 1.8v minimum on-time (buck 2) toc24 v bat 5v/div v out1 1v/div 200ns /div i out2 = 300ma fb2 line regulation vsup (v) vout (v) 10 15 20 25 30 35 40 5 0.995 1.005 1.000 1.010 0.990 0 toc22 v out2 = 1.8v maxim integrated 9 MAX17232/max17233 3.5vC36v, 2.2mhz, synchronous dual buck controller with 20a quiescent current www.maximintegrated.com
pin description pin confguration MAX17232 max17233 tqfn (5mm x 5mm) top view 26 27 25 24 10 9 11 dl1 cs1 out1 fb1 comp1 12 lx1 pgnd2 out2 fb2 dl2 comp2 fosc 1 2 en2 4 5 6 7 20 21 19 17 16 15 en1 bst1 pgood1 in extvcc agnd pgnd1 cs2 3 18 28 8 dh1 ep bias + bst2 23 13 pgood2 dh2 22 14 fsync lx2 pin name description 1 lx1 inductor connection for buck 1. connect lx1 to the switched side of the inductor. lx1 serves as the lower supply rail for the dh1 high-side gate drive. 2 dl1 low-side gate drive output for buck 1. dl1 output voltage swings from v pgnd1 to v bias . 3 pgnd1 power ground for buck 1 4 cs1 positive current-sense input for buck 1. connect cs1 to the positive terminal of the current-sense resistor. see the current limiting and current-sense inputs and current-sense measurement sections. 5 out1 output sense and negative current-sense input for buck 1. when using the internal preset 5v feedback divider (fb1 = bias), the buck uses out1 to sense the output voltage. connect out1 to the negative terminal of the current-sense resistor. see the current limiting and current-sense inputs and current-sense measurement sections. 6 fb1 feedback input for buck 1. connect fb1 to bias for the 5v fxed output or to a resistive divider between out1 and gnd to adjust the output voltage between 1v and 10v. in adjustable mode, fb1 regulates to 1v (typ). see the setting the output voltage in buck converters section. 7 comp1 buck 1 error-amplifer output. connect an rc network to comp1 to compensate buck 1. 8 bias 5v internal linear regulator output. bypass bias to gnd with a low-esr ceramic capacitor of 6.8f minimum value. bias provides the power to the internal circuitry and external loads. see the fixed 5v linear regulator (bias) section. 9 agnd signal ground for ic 10 extvcc 3.1v to 5.2v input to the switchover comparator 11 in supply input. bypass in with suffcient capacitance to supply the two out-of-phase buck converters. maxim integrated 10 MAX17232/max17233 3.5vC36v, 2.2mhz, synchronous dual buck controller with 20a quiescent current www.maximintegrated.com
pin description (continued) pin name description 12 pgood1 open-drain power-good output for buck 1. pgood1 is low if out1 is more than 15% (typ) below the normal regulation point. pgood1 asserts low during soft-start and in shutdown. pgood1 becomes high impedance when out1 is in regulation. to obtain a logic signal, pullup pgood1 with an external resistor connected to a positive voltage lower than 5.5v. place a minimum of 100? (r pgood1 ) in series with pgood1. see the voltage monitoring section for details. 13 pgood2 open-drain power-good output for buck 2. pgood2 is low if out2 is more than 15% (typ) below the normal regulation point. pgood2 asserts low during soft-start and in shutdown. pgood2 becomes high impedance when out2 is in regulation. to obtain a logic signal, pullup pgood2 with an external resistor connected to a positive voltage lower than 5.5v. 14 fsync external clock synchronization input. synchronization to the controller operating frequency ratio is 1. keep f sync a minimum of 10% greater than the maximum internal switching frequency for stable operation. see the switching frequency/external synchronization section. 15 fosc frequency setting input. connect a resistor from fosc to agnd to set the switching frequency of the dc-dc converters. 16 comp2 buck 2 error amplifer output. connect an rc network to comp2 to compensate buck 2. 17 fb2 feedback input for buck 2. connect fb2 to bias for the 3.3v fxed output or to a resistive divider between out2 and gnd to adjust the output voltage between 1v and 10v. in adjustable mode, fb2 regulates to 1v (typ). see the setting the output voltage in buck converters section. 18 out2 output sense and negative current-sense input for buck 2. when using the internal preset 3.3v feedback-divider (fb2 = bias), the buck uses out2 to sense the output voltage. connect out2 to the negative terminal of the current-sense resistor. see the current limiting and current-sense inputs and current-sense measurement sections. 19 cs2 positive current-sense input for buck 2. connect cs2 to the positive terminal of the current-sense resistor. see the current limiting and current-sense inputs and current-sense measurement sections. 20 pgnd2 power ground for buck 2 21 dl2 low-side gate drive output for buck 2. dl2 output voltage swings from v pgnd2 to v bias . 22 lx2 inductor connection for buck 2. connect lx2 to the switched side of the inductor. lx2 serves as the lower supply rail for the dh2 high-side gate drive. 23 dh2 high-side gate drive output for buck 2. dh2 output voltage swings from v lx2 to v bst2 . 24 bst2 boost capacitor connection for high-side gate voltage of buck 2. connect a high-voltage diode between bias and bst2. connect a ceramic capacitor between bst2 and lx2. see the high-side gate-driver supply (bst_) section. 25 en2 high-voltage tolerant, active-high digital enable input for buck 2. driving en2 high enables buck 2. 26 en1 high-voltage tolerant, active-high digital enable input for buck 1. driving en1 high enables buck 1. 27 bst1 boost capacitor connection for high-side gate voltage of buck 1. connect a high-voltage diode between bias and bst1. connect a ceramic capacitor between bst1 and lx1. see the high-side gate-driver supply (bst_) section. 28 dh1 high-side gate-drive output for buck 1. dh1 output voltage swings from v lx1 to v bst1 . ep exposed pad. connect the exposed pad to ground. connecting the exposed pad to ground does not remove the requirement for proper ground connections to pgnd1, pgnd2, and agnd. the exposed pad is attached with epoxy to the substrate of the die, making it an excellent path to remove heat from the ic. maxim integrated 11 MAX17232/max17233 3.5vC36v, 2.2mhz, synchronous dual buck controller with 20a quiescent current www.maximintegrated.com
detailed description the MAX17232/max17233 are dual-output switching power supplies. these devices integrate two synchronous step-down controllers and can provide two independent controlled power rails as follows: a buck controller with a fixed 5v output voltage or an adjustable 1v to 10v output voltage. a buck controller with a fixed 3.3v output voltage or an adjustable 1v to 10v output voltage. the two buck controllers can each provide up to 10a output current and are independently controllable. en1 and en2 enable the respective buck controllers. connect en1 and en2 directly to v bat , or to power- supply sequencing logic. in skip mode, with no load and only buck 2 active, the total supply current is reduced to 20a (typ). when both controllers are disabled, the total current drawn is further reduced to 8a (typ). fixed 5v linear regulator (bias) the internal circuitry of the devices requires a 5v bias supply. an internal 5v linear regulator (bias) generates this bias supply. bypass bias with a 6.8f or greater ceramic capacitor to guarantee stability under the full-load condition. the internal linear regulator can source up to 100ma (150ma under extvcc switchover, see the extvcc switchover section). use the following equation to estimate the internal current requirements for the devices: i bias = i cc + f sw (q g_dh1 + q g_dl1 + q g_dh2 + q g_dl2 ) = 10ma to 50ma (typ) where i cc is the internal supply current, 5ma (typ), f sw is the switching frequency, and q g_ is the mosfets total gate charge (specification limits at v gs = 5v). to minimize the internal power dissipation, bypass bias to an external 5v rail. extvcc switchover the internal linear regulator can be bypassed by connect - ing an external supply (3v to 5.2v) or the output of one of the buck converters to extvcc. bias internally switches to extvcc and the internal linear regulator turns off. this configuration has several advantages: it reduces the internal power dissipation of the devices. the low-load efficiency improves as the internal supply current gets scaled down proportionally to the duty cycle. if v extvcc drops below v th,extvcc = 3v (min), the internal regulator enables and switches back to bias. undervoltage lockout (uvlo) the bias input undervoltage lockout (uvlo) circuitry inhibits switching if the 5v bias supply (bias) is below its 2.9v (typ) uvlo falling threshold. once the 5v bias supply (bias) rises above its uvlo rising threshold and en1 and en2 enable the buck controllers, the controllers start switching and the output voltages begin to ramp up using soft-start. maxim integrated 12 MAX17232/max17233 3.5vC36v, 2.2mhz, synchronous dual buck controller with 20a quiescent current www.maximintegrated.com
buck controllers the devices provide two buck controllers with synchronous rectification. the step-down controllers use a pwm, current-mode control scheme. external logic- level mosfets allow for optimized load-current design. fixed-frequency operation with optimal interleaving minimizes input ripple current from the minimum to the maximum input voltages. output-current sensing provides an accurate current limit with a sense resistor or power dissipation can be reduced using lossless current sensing across the inductor. soft-start once a buck converter is enabled by driving the corresponding en_ high, the soft-start circuitry gradually ramps up the reference voltage during soft-start time (t sstart = 6ms (typ)) to reduce the input surge currents during startup. before the device can begin the soft-start, the following conditions must be met: 1) v bias exceeds the 3.4v (max) undervoltage-lockout threshold. 2) v en_ is logic-high. switching frequency/external synchronization the MAX17232 provides an internal oscillator adjustable from 1mhz to 2.2mhz. the max17233 provides an internal oscillator adjustable from 200khz to 1mhz. high- frequency operation optimizes the application for the smallest component size, trading off efficiency to higher switching losses. low-frequency operation offers the best overall efficiency at the expense of component size and board space. to set the switching frequency, connect a resistor r fosc from fosc to agnd. see toc8 and toc9 (switching frequency vs. r fosc ) in the typical operating characteristics to determine the relationship between switching frequency and r fosc . buck 1 is synchronized with the internal clock-signal rising edge, while buck 2 is synchronized with the clock-signal falling edge. the devices can be synchronized to an external clock by connecting the external clock signal to fsync. a rising edge on fsync resets the internal clock. keep the fsync frequency between 110% and 150% of the internal frequency. the fsync signal should have a 50% duty cycle. light-load effciency skip mode (v fsync = 0v) drive fsync low to enable skip mode. in skip mode, the devices stop switching until the fb voltage drops below the reference voltage. once the fb voltage has dropped below the reference voltage, the devices begin switching until the inductor current reaches 20% (skip threshold) of the maximum current defined by the inductor dcr or output shunt resistor. forced-pwm mode (v fsync = high) driving fsync high prevents the devices from entering skip mode by disabling the zero-crossing detection of the inductor current. this forces the low-side gate-driver waveform to constantly be the complement of the high- side gate-drive waveform, so the inductor current reverses at light loads and discharges the output capacitor. the benefit of forced pwm mode is to keep the switching frequency constant under all load conditions. however, forced-frequency operation diverts a considerable amount of the output current to pgnd, reducing the efficiency under light-load conditions. forced-pwm mode is useful for improving load-transient response and eliminating unknown frequency harmonics that may interfere with am radio bands. spread spectrum the max17233etis, max17233etiu, and MAX17232etis feature enhanced emi performance. they perform 6% dithering of the switching frequency to reduce peak emission noise at the clock frequency and its harmonics, making it easier to meet stringent emission limits. when using an external clock source (i.e., driving the fsync input with an external clock), spread spectrum is disabled. buck 2 switching frequency for the max17233etit and MAX17232batiu, the switching frequency of buck 2 is set to 1/2 of f sw (buck 1 switching frequency). when using these devices, the external components of buck 2 should be sized to account for the reduced switching frequency (see the design procedure section). maxim integrated 13 MAX17232/max17233 3.5vC36v, 2.2mhz, synchronous dual buck controller with 20a quiescent current www.maximintegrated.com
mosfet gate drivers (dh_ and dl_) the dh_ high-side nmosfet drivers are powered from capacitors at bst_ while the low-side drivers (dl_) are powered by the 5v linear regulator (bias). on each channel, a shoot-through protection circuit monitors the gate-to- source voltage of the external mosfets to prevent a mosfet from turning on until the complementary switch is fully off. there must be a low-resistance, low-inductance path from the dl_ and dh_ drivers to the mosfet gates for the protection circuits to work properly. follow the instructions listed to provide the necessary low-resistance and low-inductance path: use very short, wide traces (50 mils to 100 mils wide if the mosfet is 1in from the driver). it may be necessary to decrease the slew rate for the gate drivers to reduce switching noise or to compensate for low-gate charge capacitors. for the low-side drivers, use gate capacitors in the range of 1nf to 5nf from dl_ to gnd. for the high-side drivers, connect a small 5 to 10 resistor between bst_ and the bootstrap capacitor. note: gate drivers must be protected during shutdown, at the absence of the supply voltage (v bias = 0v) when the gate is pulled high either capacitively or by the leakage path on the pcb. therefore, external gate pulldown resistors are needed, to prevent making a direct path from v bat to gnd. high-side gate-driver supply (bst_) the high-side mosfet is turned on by closing an internal switch between bst_ and dh_ and transferring the boot- strap capacitors (at bst_) charge to the gate of the high- side mosfet. this charge refreshes when the high-side mosfet turns off and the lx_ voltage drops down to ground potential, taking the negative terminal of the capacitor to the same potential. at this time the bootstrap diode recharges the positive terminal of the bootstrap capacitor. the selected high-side nmosfet determines the appropriate boost capacitance values (c bst_ in the typical application circuit) according to the following equation: g bst_ bst_ q c v = ? where q g is the total gate charge of the high-side mosfet and v bst_ is the voltage variation allowed on the high-side mosfet driver after turn-on. choose v bst_ such that the available gate-drive voltage is not significantly degraded (e.g., v bst_ = 100mv to 300mv) when determining c bst_ . the boost capacitor should be a low-esr ceramic capacitor. a minimum value of 100nf works in most cases. current limiting and current-sense inputs (out_ and cs_) the current-limit circuit uses differential current-sense inputs (out_ and cs_) to limit the peak inductor current. if the magnitude of the current-sense signal exceeds the current-limit threshold (v limit1,2 = 80mv (typ)), the pwm controller turns off the high-side mosfet. the actual maximum load current is less than the peak current-limit threshold by an amount equal to half of the inductor ripple current. therefore, the maximum load capability is a function of the current-sense resistance, inductor value, switching frequency, and duty cycle (v out_ /v in ). for the most accurate current sensing, use a current- sense shunt resistor (r sh ) between the inductor and the output capacitor. connect cs_ to the inductor side of r sh and out_ to the capacitor side. dimension r sh such that the maximum inductor current (i l,max = i load,max +1/2 i ripple,pp ) induces a voltage of v limit1,2 across r sh including all tolerances. for higher efficiency, the current can also be measured directly across the inductor. this method could cause up to 30% error over the entire temperature range and requires a filter network in the current-sense circuit. see the current-sense measurement section. voltage monitoring (pgood_) the devices include several power-monitoring signals to facilitate power-supply sequencing and supervision. pgood_ can be used to enable circuits that are supplied by the corresponding voltage rail, or to turn on subsequent supplies. each pgood_ goes high (high impedance) when the corresponding regulator output voltage is in regulation. each pgood_ goes low when the corresponding regulator output voltage drops below 15% (typ) or rises above 15% (typ) of its nominal regulated voltage. connect a 10k (typ) pullup resistor from pgood_ to the relevant logic rail to level-shift the signal. pgood_ asserts low during soft-start, soft-discharge, and when either buck converter is disabled (either en1 or en2 is low). to ensure latchup immunity on the pgood1 pin, a minimum resistance of 100 should be placed between the pgood1 pin and any other external components. maxim integrated 14 MAX17232/max17233 3.5vC36v, 2.2mhz, synchronous dual buck controller with 20a quiescent current www.maximintegrated.com
thermal-overload, overcurrent, and overvoltage and undervoltage behavior thermal-overload protection thermal-overload protection limits total power dissipation in the devices. when the junction temperature exceeds +170c, an internal thermal sensor shuts down the devices, allowing them to cool. the thermal sensor turns on the devices again after the junction temperature cools by 20c. overcurrent protection if the inductor current in the MAX17232/max17233 exceeds the maximum current limit programmed at cs_ and out_, the respective driver turns off. in an overcurrent mode, this results in shorter and shorter high-side pulses. a hard short results in a minimum on-time pulse every clock cycle. choose the components so they can withstand the short-circuit current if required. overvoltage protection the devices limit the output voltage of the buck converters by turning off the high-side gate driver at approximately 115% of the regulated output voltage. the output voltage needs to come back in regulation before the high-side gate driver starts switching again. design procedure buck converter design procedure effective input voltage range in buck converters although the MAX17232/max17233 can operate from input supplies up to 36v (42v transients) and regulate down to 1v, the minimum voltage conversion ratio (v out /v in ) might be limited by the minimum controllable on-time. for proper fixed-frequency pwm operation and optimal efficiency, buck 1 and buck 2 should operate in continuous conduction during normal operating conditions. for continuous conduction, set the voltage conversion ratio as follows: out on(min) sw in v t f v > where t on(min) is 50ns (typ) and f sw is the switching frequency in hz. if the desired voltage conversion does not meet the above condition, pulse skipping occurs to decrease the effective duty cycle. decrease the switching frequency if constant switching frequency is required. the same is true for the maximum voltage conversion ratio. the maximum voltage conversion ratio is limited by the maximum duty cycle (95%). out in drop v 0.95 vv < ? where v drop = i out (r on,hs + r dcr ) is the sum of the parasitic voltage drops in the high-side path and f sw is the programmed switching frequency. during low drop operation, the devices reduce f sw to 25% (max) of the programmed frequency. in practice, the above condition should be met with adequate margin for good load- transient response. setting the output voltage in buck converters connect fb1 and fb2 to bias to enable the fixed buck controller output voltages (5v and 3.3v) set by a preset internal resistive voltage-divider connected between the output (out_) and agnd. to externally adjust the output voltage between 1v and 10v, connect a resistive divider from the output (out_) to fb_ to agnd (see the typical application circuit ). calculate r fb_1 and r fb_2 with the following equation: out_ fb_1 fb_2 fb_ v rr 1 v ?? ?? ?? ?? = ? ?? ?? ?? ?? where v fb_ = 1v (typ) (see the electrical characteristics table). dc output accuracy specifications in the electrical characteristics table refer to the error comparators threshold, v fb_ = 1v (typ). when the inductor conducts continuously, the devices regulate the peak of the output ripple, so the actual dc output voltage is lower than the slope-compensated trip level by 50% of the output ripple voltage. in discontinuous conduction mode (skip or stdby active and i out < i load(skip) ), the devices regulate the valley of the output ripple, so the output voltage has a dc regulation level higher than the error-comparator threshold. maxim integrated g 15 MAX17232/max17233 3.5vC36v, 2.2mhz, synchronous dual buck controller with 20a quiescent current www.maximintegrated.com
inductor selection in buck converters three key inductor parameters must be specified for operation with the MAX17232/max17233: inductance value (l), inductor saturation current (i sat ), and dc resistance (r dcr ). to determine the optimum inductance, knowing the typical duty cycle (d) is important. out out in in out ds(on) dcr vv d or d v v i (r r ) = = ?+ if the r dcr of the inductor and r ds(on) of the mosfet are available with v in = (v bat - v diode ). all values should be typical to optimize the design for normal operation. inductance the exact inductor value is not critical and can be adjusted in order to make trade-offs among size, cost, efficiency, and transient response requirements. lower inductor values increase lir, which minimizes size and cost and improves transient response at the cost of reduced efficiency due to higher peak currents. higher inductance values decrease lir, which increases efficiency by reducing the rms current at the cost of requiring larger output capacitors to meet load-transient specifications. the ratio of the inductor peak-to-peak ac current to dc average current (lir) must be selected first. a good initial value is a 30% peak-to-peak ripple current to average- current ratio (lir = 0.3). the switching frequency, input voltage, output voltage, and selected lir then determine the inductor value as follows: in out sw out (v v )xd l[h] f [mhz]x i x lir ? = where v in , v out , and i out are typical values (so that efficiency is optimum for typical conditions). peak inductor current inductors are rated for maximum saturation current. the maximum inductor current equals the maximum load current in addition to half of the peak-to-peak ripple current: inductor peak load(max) i ii 2 ? = + for the selected inductance value, the actual peak-to-peak inductor ripple current (i inductor ) is calculated as: out in out inductor in sw v (v v ) i v xf xl ? ?= where i inductor is in ma, l is in h, and f sw is in khz. once the peak current and the inductance are known, the inductor can be selected. the saturation current should be larger than i peak or at least in a range where the inductance does not degrade significantly. the mosfets are required to handle the same range of current without dissipating too much power. mosfet selection in buck converters each step-down controller drives two external logic-level n-channel mosfets as the circuit switch elements. the key selection parameters to choose these mosfets include the items in the following sections. threshold voltage all four n-channel mosfets must be a logic-level type with guaranteed on-resistance specifications at v gs = 4.5v. if the internal regulator is bypassed (for example: v extvcc = 3.3v), then the nmosfets should be chosen to have guaranteed on-resistance at that gate-to-source voltage. maximum drain-to-source voltage (v ds(max) ) all mosfets must be chosen with an appropriate v ds rating to handle all v in voltage conditions. maxim integrated 16 MAX17232/max17233 3.5vC36v, 2.2mhz, synchronous dual buck controller with 20a quiescent current www.maximintegrated.com
current capability the n-channel mosfets must deliver the average current to the load and the peak current during switching. choose mosfets with the appropriate average current at v gs = 4.5v or v gs = v extvcc when the internal linear regulator is bypassed. for load currents below approximately 3a, dual mosfets in a single package can be an economical solution. to reduce switching noise for smaller mosfets, use a series resistor in the bst_ path and additional gate capacitance. current-sense measurement for the best current-sense accuracy and overcurrent protection, use a 1% tolerance current-sense resistor between the inductor and output as shown in figure 1a . this configuration constantly monitors the inductor current, allowing accurate current-limit protection. use low-inductance current-sense resistors for accurate measurement. alternatively, high-power applications that do not require highly accurate current-limit protection can reduce the overall power dissipation by connecting a series rc circuit across the inductor (figure 1b) with an equivalent time constant: cshl dcr r2 rr r1 r2 ?? = ?? + ?? figure 1. current-sense configurations c out c out c in c in l nl nh input (v in ) a) output series resistor sensing dh_ lx_ dl_ gnd cs_ out_ l nl nh r2 c eq dcr r1 input (v in ) b) lossless inductor sensing dh_ lx_ dl_ gnd cs_ out_ inductor r cshl = ( ) r dcr r2 r1 + r2 r dcr = [ + ] 1 r1 1 r2 l c eq MAX17232 max17233 MAX17232 max17233 r sense maxim integrated 17 MAX17232/max17233 3.5vC36v, 2.2mhz, synchronous dual buck controller with 20a quiescent current www.maximintegrated.com
and: dcr eq l 11 r c r1 r2 ?? = + ?? ?? where r cshl is the required current-sense resistor and r dcr is the inductors series dc resistor. use the inductance and r dcr values provided by the inductor manufacturer. carefully observe the pcb layout guidelines to ensure the noise and dc errors do no corrupt the differential current- sense signals seen by cs_ and out_. place the sense resistor close to the devices with short, direct traces, making a kelvin-sense connection to the current-sense resistor. input capacitor in buck converters the discontinuous input current of the buck converter causes large input ripple currents and therefore the input capacitor must be carefully chosen to withstand the input ripple current and keep the input voltage ripple within design requirements. the 180 ripple phase operation increases the frequency of the input capacitor ripple current to twice the individual converter switching frequency. when using ripple phasing, the worst-case input capacitor ripple current is when the converter with the highest output current is on. the input voltage ripple is composed of v q (caused by the capacitor discharge) and v esr (caused by the esr of the input capacitor). the total voltage ripple is the sum of v q and v esr that peaks at the end of an on-cycle. calculate the input capacitance and esr required for a specific ripple using the following equation: ( ) esr pp load(max) out load(max) in in q sw v esr[ ] i i 2 v ix v c [f] v xf ? ? ?= ? ?? + ?? ?? ?? ?? ?? ?? = ? where: ( ) in out out pp in sw v v xv i v xf xl ? ? ?= i load(max) is the maximum output current in a, i p-p is the peak-to-peak inductor current in a, f sw is the switching frequency in mhz, and l is the inductor value in h. the internal 5v linear regulator (bias) includes an output uvlo with hysteresis to avoid unintentional chattering during turn-on. use additional bulk capacitance if the input source impedance is high. at lower input voltage, additional input capacitance helps avoid possible under - shoot below the undervoltage lockout threshold during transient loading. output capacitor in buck converters the actual capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. the capacitor is usually selected by esr and the voltage rating rather than by capacitance value. when using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent v sag and v soar from causing problems during load transients. generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem (see the transient considerations section). however, low-capacity filter capacitors typically have high-esr zeros that can affect the overall stability. the total voltage sag (v sag ) can be calculated as follows: 2 load(max) sag out in max out load(max) out l( i ) v 2c ((v d ) v ) i (t t) c ? = ? ? ?? + the amount of overshoot (v soar ) during a full-load to no-load transient due to stored inductor energy can be calculated as: 2 load(max) soar out out (i )l v 2c v ? esr considerations the output filter capacitor must have low enough equivalent series resistance (esr) to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. when using high-capacitance, low-esr capacitors, the filter capacitors esr dominates the output voltage ripple. so the output capacitors size depends on the maximum esr required to meet the output-voltage ripple (v ripple(p-p) ) specifications: ripple(p p) load(max) v esr xi x lir ? = maxim integrated 18 MAX17232/max17233 3.5vC36v, 2.2mhz, synchronous dual buck controller with 20a quiescent current www.maximintegrated.com
in standby mode, the inductor current becomes discontinuous, with peak currents set by the idle-mode current-sense threshold (v cs,skip = 26mv (typ)). transient considerations the output capacitor must be large enough to absorb the inductor energy while transitioning from no-load to full-load condition without tripping the overvoltage fault protection. the total output voltage sag is the sum of the voltage sag while the inductor is ramping up and the voltage sag before the next pulse can occur. therefore: ( ) ( ) 2 load(max) out sag in max out load(max) sag li c 2v (v xd v ) i tt v ? = ? ? ?? + where d max is the maximum duty factor (approximately 95%), l is the inductor value in h, c out is the output capacitor value in f, t is the switching period (1/f sw ) in s, and t equals (v out /v in ) x t. the MAX17232/max17233 use a peak current-mode control scheme that regulates the output voltage by forcing the required current through the external inductor, so the controller uses the voltage drop across the dc resistance of the inductor or the alternate series current- sense resistor to measure the inductor current. current- mode control eliminates the double pole in the feedback loop caused by the inductor and output capacitor resulting in a smaller phase shift and requiring less elaborate error-amplifier compensation than voltage-mode control. a single series resistor (r c ) and capacitor (c c ) is all that is required to have a stable, high-bandwidth loop in applications where ceramic capacitors are used for output filtering (see figure 2 ). for other types of capacitors, due to the higher capacitance and esr, the frequency of the zero created by the capacitance and esr is lower than the desired closed-loop crossover frequency. to stabilize a non-ceramic output capacitor loop, add another compensation capacitor (c f ) from comp to agnd to cancel this esr zero. the basic regulator loop is modeled as a power modulator, output feedback divider, and an error amplifier as shown in figure 2 . the power modulator has a dc gain set by g mc x r load , with a pole and zero pair set by r load , the output capacitor (c out ), and its esr. the loop response is set by the following equations: mod(dc) mc load gain g r = where r load = v out /i lout(max) in and g mc =1/(a v_cs x r dc ) in s. a v_cs is the voltage gain of the current-sense amplifier and is typically 11v/v. r dc is the dc resistance of the inductor or the current-sense resistor in . in a current-mode step-down converter, the output capacitor and the load resistance introduce a pole at the following frequency: pmod out load 1 f 2c r = the unity gain frequency of the power stage is set by c out and g mc : mc ugainpmod out g f 2c = the output capacitor and its esr also introduce a zero at: zmod out 1 f 2 esr c = when c out is composed of n identical capacitors in parallel, the resulting c out = nxc out(each) , and esr = esr (each) /n. note that the capacitor zero for a parallel combination of alike capacitors is the same as for an individual capacitor. the feedback voltage-divider has a gain of gain fb = v fb /v out , where v fb is 1v (typ). figure 2. compensation network c s_ o u t_ fb_ r1 r esr c c c f r c r2 v ref c out g mc = 1/ (a vc s x r d c ) c u r r en t mo d e po w er mo d u l at i o n er r o r am p c o m p_ g mea = 1 2 0 0 s 3 0m? maxim integrated 19 MAX17232/max17233 3.5vC36v, 2.2mhz, synchronous dual buck controller with 20a quiescent current www.maximintegrated.com
the transconductance error amplifier has a dc gain of gain ea(dc) = g m,ea x r out,ea , where g m,ea is the error amplifier transconductance, which is 1200s (typ), and r out,ea is the output resistance of the error amplifier, which is 30m (typ) (see the electrical characteristics table.) a dominant pole (f dpea ) is set by the compensation capacitor (c c ) and the amplifier output resistance (r out,ea ). a zero (f zea ) is set by the compensation resistor (r c ) and the compensation capacitor (c c ). there is an optional pole (f pea ) set by c f and r c to cancel the output capacitor esr zero if it occurs near the crossover frequency (f c , where the loop gain equals 1 (0db)). thus: dpea c out,ea c 1 f 2 c (r r ) = + zea cc 1 f 2c r = pea fc 1 f 2c r = the loop-gain crossover frequency (f c ) should be set below 1/5th of the switching frequency and much higher than the power-modulator pole (f pmod ). select a value for f c in the range: sw pmod c f ff 5 << at the crossover frequency, the total loop gain must be equal to 1. so: cc fb mod(f ) ea(f ) out v gain gain 1 v = c ea(f ) m,ea c gain g r = c pmod mod(f ) mod(dc ) c f gain gain f = therefore: c fb mod(f ) m,ea c out v gain g r 1 v = solving for r c : c out c m,ea fb mod(f ) v r g v gain = set the error-amplifier compensation zero formed by r c and c c at the f pmod . calculate the value of c c as follows: c 1 c 2f r pmod c = if f zmod is less than 5 x f c , add a second capacitor c f from comp to agnd. the value of c f is: f 1 c 2f r zmod c = as the load current decreases, the modulator pole also decreases; however, the modulator gain increases accordingly and the crossover frequency remains the same. below is a numerical example to calculate the compensation network component values of figure 2: a v_cs = 11v/v r dcr = 15m g mc = 1/(a v_cs x r dc ) = 1/(11 x 0.015) = 6.06 v out = 5v i out(max) = 5.33a r load = v out /i out(max) = 5v/5.33a = 0.9375 c out = 2x47f = 94f esr = 9m/2 = 4.5m f sw = 26.4/65.5k = 0.403mhz mod(dc ) gain 6.06 0.9375 5.68 == pmod 1 f 1.8khz 2 94f 0.9375 = sw pmod c f ff 5 << c 1.8khz f 80.6khz << select f c = 40khz zmod 1 f 376khz 2 4.5m 94f = ? since f zmod >f c : r c 16k c c 5.6nf c f 27pf maxim integrated 20 MAX17232/max17233 3.5vC36v, 2.2mhz, synchronous dual buck controller with 20a quiescent current www.maximintegrated.com
applications information layout recommendations careful pcb layout is critical to achieve low switching losses and clean, stable operation. the switching power stage requires particular attention (figure 3 ). if possible, mount all the power components on the top side of the board, with their ground terminals flush against one another. follow these guidelines for good pcb layout: keep the high-current paths short, especially at the ground terminals. this practice is essential for stable, jitter-free operation. keep the power traces and load connections short. this practice is essential for high efficiency. using thick copper pcbs (2oz vs. 1oz) can enhance full load efficiency by 1% or more. minimize current-sensing errors by connecting cs_ and out_. use kelvin sensing directly across the current-sense resistor (r sense_ ). route high-speed switching nodes (bst_, lx_, dh_, and dl_) away from sensitive analog areas (fb_, cs_, and out_). layout procedure 1) place the power components first, with ground terminals adjacent (low-side fet, cin, cout_, and schottky). if possible, make all these connections on the top layer with wide, copper-filled areas. 2) mount the controller ic adjacent to the low-side mosfet, preferably on the back side opposite nl_ and nh_ to keep lx_, gnd, dh_, and the dl_ gate drive lines short and wide. the dl_ and dh_ gate traces must be short and wide (50 mils to 100 mils wide if the mosfet is 1in from the controller ic) to keep the driver impedance low and for proper adaptive dead-time sensing. 3) group the gate-drive components (bst_ diode and capacitor and ldo bypass capacitor bias) together near the controller ic. be aware that gate currents of up to 1a flow from the bootstrap capacitor to bst_, from dh_ to the gate of the external hs switch and from the lx_ pin to the inductor. up to 100ma of current flow from the bias capacitor through the bootstrap diode to the bootstrap capacitor. dimension those traces accordingly. 4) make the dc-dc controller ground connections as shown in figure 3 . this diagram can be viewed as having two separate ground planes: power ground, where all the high-power components go; and an analog ground plane for sensitive analog components. the analog ground plane and power ground plane must meet only at a single point directly under the ic. 5) connect the output power planes directly to the output filter capacitor positive and negative terminals with multiple vias. place the entire dc-dc converter circuit as close to the load as is practical. figure 3. layout example inductor c out c out c in input kelvin-sense vias under the sense resistor (refer to the evaluation kit) ground output low-side n-channel mosfet (nh) high-side n-channel mosfet (nl) maxim integrated 21 MAX17232/max17233 3.5vC36v, 2.2mhz, synchronous dual buck controller with 20a quiescent current www.maximintegrated.com
block diagram eamp1 pgood comp pgood1 comp1 pgood low level pgood high level fb1 out1 cs1 en1 80 mv(typ) max differential input feedback select logic ref = 1v current-limit threshold oscillator tied high (pwm mode) tied low (skip mode) clk2 clk1 internal soft-start slope comp logic clk 180 out-of-phase internal linear regulator switchover dc-dc1 control logic zero cross comp csa1 ep cl pwm1 lx1 lx2 lx1 bias clk1 step-down dc-dc1 gate drive logic en1 bst1 dh1 lx1 dl1 pgnd1 pgnd2 bias extvcc if 3.1v < v extvcc < 5.2v pwm1 zx1 spread spectrum option available with internal clock only external clock input fsync select logic dc-dc2 control logic same as dc-dc1 above fsync fosc comp2 fb2 out2 cs2 en2 pgood2 agnd in clk2 step-down dc-dc2 gate drive logic en2 bst2 dh2 lx2 dl2 pwm2 zx2 lx2 MAX17232 max17233 maxim integrated 22 MAX17232/max17233 3.5vC36v, 2.2mhz, synchronous dual buck controller with 20a quiescent current www.maximintegrated.com
note: insert the desired suffix letter (from selector guide) into the blank to indicate buck 2 switching frequency and spread spectrum. +denotes a lead(pb)-free/rohs-compliant package. *ep = exposed pad. package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: bicmos selector guide ordering information part buck 1 switching frequency (f sw1 ) buck 2 switching frequency (f sw2 ) spread spectrum (%) max17233 etir+ 1mhz to 2.2mhz f sw1 max17233etis+ 1mhz to 2.2mhz f sw1 6 MAX17232 etir+ 200khz to 1mhz f sw1 MAX17232etis+ 200khz to 1mhz f sw1 6 part temp range pin-package max17233 eti_+ -40c to +85c 28 tqfn-ep* MAX17232 eti_+ -40c to +85c 28 tqfn-ep* package type package code outline no. land pattern no. 28 tqfn-ep t2855+5 21-0140 90-0025 maxim integrated 23 MAX17232/max17233 3.5vC36v, 2.2mhz, synchronous dual buck controller with 20a quiescent current www.maximintegrated.com
revision history revision number revision date description pages changed 0 2/16 initial release ? 2016 maxim integrated products, inc. 24 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifcations without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. MAX17232/max17233 3.5vC36v, 2.2mhz, synchronous dual buck controller with 20a quiescent current for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com.

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